Name: Intel ARCHITECTURE IA-32
Brand: Intel
Rating: 5 (1 reviews)

To Next Page

To Previous Page

IA-32 Intel® Architecture Optimization

2-86

In some situations, the byte count of the data to operate is known by the

context (versus from a parameter passed from a call). One can take a

simpler approach than those required for a general-purpose library

routine. For example, if the byte count is also small, using rep

movsb/stosb with count less than four can ensure good address

alignment and loop-unrolling to finish the remaining data; using

movsd/stosd can reduce the overhead associated with iteration.

Using a REP prefix with string move instructions can provide high

performance in the situations described above. However, using a REP

prefix with string scan instructions (scasb, scasw, scasd, scasq) or

compare instructions (cmpsb, cmpsw, smpsd, smpsq) is not

recommended for high performance. Consider using SIMD instructions

instead.

Address Calculations

Use the addressing modes for computing addresses rather than using the

general-purpose computation. Internally, memory reference instructions

can have four operands:

• relocatable load-time constant

• immediate constant

• base register

• scaled index register

In the segmented model, a segment register may constitute an additional

operand in the linear address calculation. In many cases, several integer

instructions can be eliminated by fully using the operands of memory

references.

Questions and Answers:

Need help?

Do you have a question about the Intel ARCHITECTURE IA-32 and is the answer not in the manual?

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)