Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
6-50
The instruction, temp = a[kk+CACHESIZE], is used to ensure the page
table entry for array, and
a is entered in the TLB prior to prefetching.
This is essentially a prefetch itself, as a cache line is filled from that
memory location with this instruction. Hence, the prefetching starts
from
kk+4 in this loop.
This example assumes that the destination of the copy is not temporally
adjacent to the code. If the copied data is destined to be reused in the
near future, then the streaming store instructions should be replaced
with regular 128 bit stores(
_mm_store_ps). This is required because the
implementation of streaming stores on Pentium 4 processor writes data
directly to memory, maintaining cache coherency.
Using 16-byte Streaming Stores and Hardware Prefetch
An alternate technique for optimizing a large region memory copy is to
take advantage of hardware prefetcher, 16-byte streaming stores, and
apply a segmented approach to separate bus.read and write transactions
(see “Minimizing Bus Latency” in Chapter 2). This technique employs
two stages. In the first stage, a block of data is read from memory to the
cache sub-system. In the second stage, cached data are written to their
destination using streaming stores.
Example 6-12 Memory Copy Using Hardware Prefetch and Bus Segmentation
void block_prefetch(void *dst,void *src)
{ _asm {
mov edi,dst
mov esi,src
mov edx,SIZE
align 16
main_loop:
xor ecx,ecx
align 16
}

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)