Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
D-10
Inlined Assembly and ebx
When using aligned frames, the ebx register generally should not be
modified in inlined assembly blocks since
ebx is used to keep track of
the argument block. Programmers may modify
ebx only if they do not
need to access the arguments and provided they save
ebx and restore it
before the end of the function (since
esp is restored relative to ebx in the
function’s epilog).
For additional information on the use of
ebx in inline assembly code and
other related issues, see relevant application notes in the Intel
Architecture Performance Training Center.
CAUTION. Do not use the ebx register in inline
assembly functions that use dynamic stack alignment
for double, __m64, and __m128 local variables unless
you save and restore
ebx each time you use it. The
Intel C++ Compiler uses the
ebx register to control
alignment of variables of these types, so the use of
ebx,
without preserving it, will cause unexpected program
execution.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)