Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-10
The pack instructions always assume that the source operands are
signed numbers. The result in the destination register is always defined
by the pack instruction that performs the operation. For example, the
packssdw instruction packs each of the two signed 32-bit values of the
two sources into four saturated 16-bit signed values in the destination
register. The
packuswb instruction, on the other hand, packs each of the
four signed 16-bit values of the two sources into eight saturated eight-bit
unsigned values in the destination. A complete specification of the
MMX instruction set can be found in the Intel Architecture MMX
Technology Programmer’s Reference Manual, order number 243007.
Interleaved Pack without Saturation
Example 4-5 is similar to Example 4-4 except that the resulting words
are not saturated. In addition, in order to protect against overflow, only
the low order 16 bits of each doubleword are used in this operation.
Example 4-4 Interleaved Pack with Saturation
; Input:
MM0 signed source1 value
; MM1 signed source2 value
; Output:
MM0 the first and third words contain the
; signed-saturated doublewords from MM0,
; the second and fourth words contain
; signed-saturated doublewords from MM1
;
packssdw MM0, MM0 ; pack and sign saturate
packssdw MM1, MM1 ; pack and sign saturate
punpcklwd MM0, MM1 ; interleave the low-end 16-bit
; values of the operands

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)