Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-6
When two applications are employed as part of a multi-tasking
workload, there is little synchronization overhead between these two
processes. It is also important to ensure each application has minimal
synchronization overhead within itself.
An application that uses lengthy spin loops for intra-process
synchronization is less likely to benefit from Hyper-Threading
Technology in a multi-tasking workload. This is because critical
resources will be consumed by the long spin loops.
Programming Models and Multithreading
Parallelism is the most important concept in designing a multithreaded
application and realizing optimal performance scaling with multiple
processors. An optimized multithreaded application is characterized by
large degrees of parallelism or minimal dependencies in the following
areas:
• workload
• thread interaction
• hardware utilization
The key to maximizing workload parallelism is to identify multiple
tasks that have minimal inter-dependencies within an application and to
create separate threads for parallel execution of those tasks.
Concurrent execution of independent threads is the essence of deploying
a multithreaded application on a multiprocessing system. Managing the
interaction between threads to minimize the cost of thread
synchronization is also critical to achieving optimal performance
scaling with multiple processors.
Efficient use of hardware resources between concurrent threads requires
optimization techniques in specific areas to prevent contentions of
hardware resources. Coding techniques for optimizing thread
synchronization and managing other hardware resources are discussed
in subsequent sections.
Parallel programming models are discussed next.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)