Intel ARCHITECTURE IA-32 User Manual

Coding for SIMD Architectures 3
3-27
Improving Memory Utilization
Memory performance can be improved by rearranging data and
algorithms for SSE 2, SSE, and MMX technology intrinsics. The
methods for improving memory performance involve working with the
following:
• Data structure layout
• Strip-mining for vectorization and memory utilization
• Loop-blocking
Using the cacheability instructions, prefetch and streaming store, also
greatly enhance memory utilization. For these instructions, see
Chapter 6, “Optimizing Cache Usage.”
Data Structure Layout
For certain algorithms, like 3D transformations and lighting, there are
two basic ways of arranging the vertex data. The traditional method is
the array of structures (AoS) arrangement, with a structure for each
vertex (see Example 3-14). However this method does not take full
advantage of the SIMD technology capabilities.
The best processing method for code using SIMD technology is to
arrange the data in an array for each coordinate (see Example 3-15).
This data arrangement is called structure of arrays (SoA).
Example 3-14 AoS Data Structure
typedef struct{
float x,y,z;
int a,b,c;
. . .
} Vertex;
Vertex Vertices[NumOfVertices];

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)