Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
3-26
In C++ (but not in C) it is also possible to force the alignment of a
class/struct/union type, as in the code that follows:
struct __declspec(align(16)) my_m128
{
float f[4];
};
But, if the data in such a class is going to be used with the Streaming
SIMD Extensions or Streaming SIMD Extensions 2, it is preferable to
use a
union to make this explicit. In C++, an anonymous union can be
used to make this more convenient:
class my_m128 {
union {
__
m128 m;
float f[4];
};
};
In this example, because the union is anonymous, the names, m and f,
can be used as immediate member names of
my__m128. Note that
__declspec(align) has no effect when applied to a class, struct, or
union member in either C or C++.
Alignment by Using
__m64 or double Data. In some cases, for better
performance, the compiler will align routines with
__m64 or double
data to 16-bytes by default. The command-line switch,
-Qsfalign16,
can be used to limit the compiler to only align in routines that contain
128-bit data. The default behavior is to use
-Qsfalign8, which instructs
to align routines with 8- or 16-byte data types to 16-bytes.
For more details, see relevant Intel application notes in the Intel
Architecture Performance Training Center provided with the SDK and
the Intel® C++ Compiler User’s Guide.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)