Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
E-4
Memory access plays a pivotal role in prefetch scheduling. For more
understanding of a memory subsystem, consider Streaming SIMD
Extensions and Streaming SIMD Extensions 2 memory pipeline
depicted in Figure E-1.
Assume that three cache lines are accessed per iteration and four chunks
of data are returned per iteration for each cache line. Also assume these
3 accesses are pipelined in memory subsystem. Based on these
assumptions,
T
b
= 3 * 4 = 12 FSB cycles.
Figure E-1 Pentium II, Pentium III and Pentium 4 Processors Memory Pipeline
Sketch
1 2 3 4
1
1 2 3 4
1
1 2 3 4
1
T
l
T
b
:
L2 lookup miss latency
:
Memory page access leadoff latency
:
Latency for 4 chunks returned per line
2 3
1
4

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)