Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-39
An example of a loop-carried dependence chain is shown in
Example 2-17.
Data Layout Optimizations
User/Source Coding Rule 2. (H impact, M generality) Pad data structures
defined in the source code so that every data element is aligned to a natural
operand size address boundary.
If the operands are packed in a SIMD instruction, align to the packed
element size (64-bit or 128-bit).
Align data by providing padding inside structures and arrays.
Programmers can reorganize structures and arrays to minimize the
amount of memory wasted by padding. However, compilers might not
have this freedom. The C programming language, for example, specifies
the order in which structure elements are allocated in memory. Section
“Stack and Data Alignment” of Chapter 3, and Appendix D, “Stack
Alignment”, further defines the exact storage layout.
Example 2-18 shows how a data structure could be rearranged to reduce
its size.
Example 2-17 An Example of Loop-carried Dependence Chain
for (i=0; i<MAX; i++) {
a[i] = b[i] * foo;
foo = a[i]/3;
} // foo is a loop-carried dependence
Example 2-18 Rearranging a Data Structure
struct unpacked { /* fits in 20 bytes due to padding */
int a;
char b;
int c;
char d;
int e;
}
struct packed { /* fits in 16 bytes */

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)