Intel ARCHITECTURE IA-32 User Manual

Optimizing Cache Usage 6
6-31
Figure 6-5 Memory Access Latency and Execution With Prefetch
2 Load streams, 1 store stream
50
100
150
200
250
300
350
54 108 144 192 240 336 390
Computations per loop
Effective loop latency
0.00%
10.00%
20.00%
30.00%
40.00%
50.00%
60.00%
70.00%
80.00%
90.00%
100.00%
% of Bus Utilized
16 32 64 128 none
% Bus Utilization
One load and one store stream
0
50
100
150
200
250
300
350
48 108 144 192 240 336 408
Com putations pe r loop
Effective loop latency
0.00%
10.00%
20.00%
30.00%
40.00%
50.00%
60.00%
70.00%
80.00%
90.00%
100.00%
% of Bus Utilization
16_por 32_por 64_por 128_por None_por
% Bus Utilization

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)