Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
E-10
Memory Throughput Bound (Case: T
b
>= T
c
)
When the application or loop is memory throughput bound, the memory
latency is no way to be hidden. Under such circumstances, the burst
latency is always greater than the compute latency. Examine Figure E-5.
The following relationship calculates the prefetch scheduling distance
(or prefetch iteration distance) for the case when memory throughput
latency is greater than the compute latency.
Apparently, the iteration latency is dominant by the memory throughput
and you cannot do much about it. Typically, data copy from one space to
another space, for example, graphics driver moving data from writeback
Figure E-5 Memory Throughput Bound Pipeline
i
Execution cycles
Execution pipeline
i+pid
T
c
δ
f
T
c
T
c
T
c
i+pid+1 i+pid+2 i+pid+3
Front-Side Bus
T
l
T
b
T
l
T
b
T
l
T
b
T
l
T
b
T
l
T
b
δ
f
δ
f
δ
f

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)