Intel ARCHITECTURE IA-32 User Manual

Coding for SIMD Architectures 3
3-39
Recommendation: When targeting code generation for Intel Core Solo
and Intel Core Duo processors, favor instructions consisting of
two-micro-ops over those with more than two micro-ops.
Tuning the Final Application
The best way to tune your application once it is functioning correctly is
to use a profiler that measures the application while it is running on a
system. VTune analyzer can help you determine where to make changes
in your application to improve performance. Using the VTune analyzer
can help you with various phases required for optimized performance.
See “Intel® VTune™ Performance Analyzer” in Appendix A for more
details on how to use the VTune analyzer. After every effort to optimize,
you should check the performance gains to see where you are making
your major optimization gains.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)