Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
E-8
The following formula shows the relationship among the parameters:
It can be seen from this relationship that the iteration latency is equal to
the computation latency, which means the memory accesses are
executed in background and their latencies are completely hidden.
Compute Bound (Case: T
l
+ T
b
> T
c
> T
b
)
Now consider the next case by first examining Figure E-4.
Figure E-4 Another Compute Bound Execution Pipeline
Execution cycles
Front-Side Bus
Execution pipeline
i
i+1
i+2
i+3
i
i+1
i+2
i+3
T
c
T
c
T
c
T
c
T
l
T
b
T
l
T
b
T
l
T
b
T
l
T
b
δ
f
δ
f
T
c
δ
f
i+4

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)