Intel ARCHITECTURE IA-32 User Manual

Multi-Core and Hyper-Threading Technology 7
7-35
reads. An approximate working guideline for software to operate below
bus saturation is to check if bus read queue depth is significantly
below 5.
Some MP platform may have a chipset that provides two buses, with
each bus servicing one or more physical processors. The guidelines for
conserving bus bandwidth described above also applies to each bus
domain.
Understand the Bus and Cache Interactions
Be careful when parallelizing code sections with data sets that results in
the total working set exceeding the second-level cache and /or
consumed bandwidth exceeding the capacity of the bus. On an Intel
Core Duo processor, if only one thread is using the second-level cache
and / or bus, then it is expected to get the maximum benefit of the cache
and bus systems because the other core does not interfere with the
progress of the first thread. However, if two threads use the second-level
cache concurrently, there may be performance degradation if one of the
following conditions is true:
• Their combined working set is greater than the second-level cache
size
• Their combined bus usage is greater than the capacity of the bus
• They both have extensive access to the same set in the second-level
cache, and at least one of the threads writes to this cache line
To avoid these pitfalls, multi-threading software should try to
investigate parallelism schemes in which only one of the threads access
the second-level cache at a time, or where the second-level cache and
the bus usage does not exceed their limits.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)