Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-11
Non-Interleaved Unpack
The unpack instructions perform an interleave merge of the data
elements of the destination and source operands into the destination
register. The following example merges the two operands into the
destination registers without interleaving. For example, take two
adjacent elements of a packed-word data type in
source1 and place this
value in the low 32 bits of the results. Then take two adjacent elements
of a packed-word data type in
source2 and place this value in the high
32 bits of the results. One of the destination registers will have the
combination illustrated in Figure 4-3.
Example 4-5 Interleaved Pack without Saturation
; Input:
; MM0 signed source value
; MM1 signed source value
; Output:
; MM0 the first and third words contain the
; low 16-bits of the doublewords in MM0,
; the second and fourth words contain the
; low 16-bits of the doublewords in MM1
pslld MM1, 16 ; shift the 16 LSB from each of the
; doubleword values to the 16 MSB
; position
pand MM0, {0,ffff,0,ffff}
; mask to zero the 16 MSB
; of each doubleword value
por MM0, MM1 ; merge the two operands

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)