Intel ARCHITECTURE IA-32 User Manual

Stack Alignment D
D-3
As an optimization, an alternate entry point can be created that can be
called when proper stack alignment is provided by the caller. Using call
graph profiling of the VTune analyzer, calls to the normal (unaligned)
entry point can be optimized into calls to the (alternate) aligned entry
point when the stack can be proven to be properly aligned. Furthermore,
a function alignment requirement attribute can be modified throughout
the call graph so as to cause the least number of calls to unaligned entry
points. As an example of this, suppose function F has only a stack
alignment requirement of 4, but it calls function G at many call sites,
and in a loop. If G’s alignment requirement is 16, then by promoting F’s
alignment requirement to 16, and making all calls to G go to its aligned
entry point, the compiler can minimize the number of times that control
passes through the unaligned entry points. Example D-1 and
Figure D-1 Stack Frames Based on Alignment Type
Parameter
Pointer
EBP
ESP
EBP-based Aligned Frame
Parameters
Return Address
Padding
Previous EBP
Local Variables and
Spill Slots
Parameter Passing
Space
EBP-frame Saved
Register Area
Return Address 1
SEH/CEH Record
Parameter
Pointer
ESP
ESP-based Aligned Frame
Parameters
Return Address
Padding
Register Save Area
Local Variables and
Spill Slots
__cdecl Parameter
Passing Space
__stdcall Parameter
Passing Space

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)