Intel ARCHITECTURE IA-32 User Manual

Stack Alignment D
D-6
Aligned ebp-Based Stack Frames
In ebp-based frames, padding is also inserted immediately before the
return address. However, this frame is slightly unusual in that the return
address may actually reside in two different places in the stack. This
occurs whenever padding must be added and exception handling is in
effect for the function. Example D-2 shows the code generated for this
type of frame. The stack location of the return address is aligned 12 mod
16. This means that the value of
ebp always satisfies the condition (ebp
& 0x0f) == 0x08
. In this case, the sum of the sizes of the return
address, the previous
ebp, the exception handling record, the local
variables, and the spill area must be a multiple of 16 bytes. In addition,
the parameter passing space must be a multiple of 16 bytes. For a call to
a
stdcall function, it is necessary for the caller to reserve some stack
space if the size of the parameter block being pushed is not a multiple
of 16.
NOTE. A. Aligned entry points assume that parameter
block beginnings are aligned. This places the stack
pointer at a 12 mod 16 boundary, as the return pointer
has been pushed. Thus, the unaligned entry point must
force the stack pointer to this boundary.
B. The code at the common label assumes the
stack is at an 8 mod 16 boundary, and adds sufficient
space to the stack so that the stack pointer is aligned to
a 0 mod 16 boundary.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)