Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
E-6
No Preloading or Prefetch
The traditional programming approach does not perform data
preloading or prefetch. It is sequential in nature and will experience
stalls because the memory is unable to provide the data immediately
when the execution pipeline requires it. Examine Figure E-2.
As you can see from Figure E-2, the execution pipeline is stalled while
waiting for data to be returned from memory. On the other hand, the
front side bus is idle during the computation portion of the loop. The
memory access latencies could be hidden behind execution if data could
be fetched earlier during the bus idle time.
Further analyzing Figure E-2,
• assume execution cannot continue till last chunk returned and
• δ
f
indicates flow data dependency that stalls the execution pipelines
With these two things in mind the iteration latency (il) is computed as
follows:
Figure E-2 Execution Pipeline, No Preloading or Prefetch
Execution cycles
Execution
pipeline
(i+1)
th
iteration
T
l
T
b
δ
f
T
c
- T
Δ
T
Δ
T
l
T
b
δ
f
T
Δ
T
c
- T
Δ
Front-Side
Bus
i
th
iteration
issue loads
issue loads
Execution units idle
Execution units idle
FSB idle
il T
c
T+
l
T
b
+≅

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)