Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Processor Family Overview
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Execution Core
The core can dispatch up to six µops per cycle, provided the µops are
ready to execute. Once the µops are placed in the queues waiting for
execution, there is no distinction between instructions from the two
logical processors. The execution core and memory hierarchy is also
oblivious to which instructions belong to which logical processor.
After execution, instructions are placed in the re-order buffer. The
re-order buffer decouples the execution stage from the retirement stage.
The re-order buffer is partitioned such that each uses half the entries.
Retirement
The retirement logic tracks when instructions from the two logical
processors are ready to be retired. It retires the instruction in program
order for each logical processor by alternating between the two logical
processors. If one logical processor is not ready to retire any
instructions, then all retirement bandwidth is dedicated to the other
logical processor.
Once stores have retired, the processor needs to write the store data into
the level-one data cache. Selection logic alternates between the two
logical processors to commit store data to the cache.
Multi-Core Processors
The Intel Pentium D processor and the Pentium Processor Extreme
Edition introduce multi-core features in the IA-32 architecture. These
processors enhance hardware support for multi-threading by providing
two processor cores in each physical processor package. The Dual-core
Intel Xeon and Intel Core Duo processors also provide two processor
cores in a physical package.
The Intel Pentium D processor provides two logical processors in a
physical package, each logical processor has a separate execution core
and a cache hierarchy. The Dual-core Intel Xeon processor and the Intel

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)