Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-54
Example 7-12 Assembling a Look up Table to Manage Affinity Masks and
Schedule Threads to Each Core First
AFFINITYMASK LuT[64]; // A Lookup table to retrieve the affinity
// mask we want to use from the thread
// scheduling sequence index.
int index =0; // Index to scheduling sequence.
j = 0;
/ Assemble the sequence for first LP consecutively to different core.
while (j < NumStartedLPs) {
// Determine the first LP in each core.
if( ! apic_conf [j ].smt) { // This is the first LP in a core
// supporting HT.
LuT[index++] = apic_conf[j].affinitymask;
}
j++;
}
/// Now the we have assigned each core to consecutive indices,
// we can finish the table to use the rest of the
// LPs in each core.
nThreadsPerCore = MaxLPPerPackage()/MaxCoresPerPackage();
for (i = 0 ; i < nThreadsPerCore; i ++) {
for (j = 0 ; j < NumStartedLPs; j += nThreadsPerCore) {
// Set the affinity binding for another logical
// processor in each core.
if( apic_conf[ i+j ].SMT) {
LuT[ index++] = apic_id[ i+j ].affinitymask;
}
}
}
}

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)