Intel ARCHITECTURE IA-32 User Manual

Application Performance Tools A
A-11
different events at a time. The number of the events that the VTune
analyzer can collect at once on the Pentium 4 and Intel Xeon processor
depends on the events selected.
Event-based samples are collected after a specific number of processor
events have occurred. The samples can then be attributed to the different
processes, threads, software modules, functions, and lines of code
running on the system.
Workload Characterization
Using event-based sampling and processor-specific events can provide
useful insights into the nature of the interaction between a workload and
the microarchitecture. A few metrics useful for workload
characterization are given below:
Retirement Throughput: Table B-1 includes several ratios (measured
from processor-specific events) that characterize the effective
throughput of instructions (or μops) at the retirement stage. For
example, UPC measure μops throughput at the retirement stage, which
can be compared to the peak retirement bandwidth of the
microarchitecture to evaluate the degree of extractable instruction-level
parallelism in the workload. Non-halted CPI and Non-Sleep CPI
measure the effective instruction execution throughput at the retirement
stage. The former is usually set up for measurement on a per logical
processor basis, while the latter is always set up for measurement on a
per processor core basis (if a processor core provides two logical
processors).
Data Traffic Locality: The processor event “Bus Reads Underway
from the Processors” be used to characterize the dominant data traffic
locality being the memory sub-system or the cache hierarchy. By
customizing this event using the “Edit Event” dialog box to enable the
“COMPARE” bit in the CCCR, one can measure the effective duration
of bus read traffic from the memory sub-system. If the ratio of this

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)