Intel ARCHITECTURE IA-32 User Manual

IA-32 Instruction Latency and Throughput C
C-7
Table C-2 Streaming SIMD Extension 2 128-bit Integer Instructions
Instruction Latency
1
Throughput
Execution
Unit
2
CPUID 0F3n 0F2n 0x69n 0F3n 0F2n 0x69n 0F2n
CVTDQ2PS
3
xmm, xmm 55 22 FP_ADD
CVTPS2DQ
3
xmm, xmm 553+122 2FP_ADD
CVTTPS2DQ
3
xmm, xmm 553+122 2FP_ADD
MOVD xmm, r32 6 6 1 2 2 2 MMX_MISC,
MMX_SHFT
MOVD r32, xmm 10 10 1+1 1 1 2 FP_MOVE,
FP_MISC
MOVDQA xmm, xmm 6 6 1 1 1 1 FP_MOVE
MOVDQU xmm, xmm 6 6 1 1 1 1 FP_MOVE
MOVDQ2Q mm, xmm 8 8 1 2 2 1 FP_MOVE,
MMX_ALU
MOVQ2DQ xmm, mm 8 8 1 2 2 1 FP_MOVE,
MMX_SHFT
MOVQ xmm, xmm 2 2 1 2 2 1 MMX_SHFT
PACKSSWB/PACKSSDW/
PACKUSWB xmm, xmm
4 4 2+1 2 2 2 MMX_SHFT
PADDB/PADDW/PADDD
xmm, xmm
2 2 1 2 2 1 MMX_ALU
PAD DS B/PA DD S W /
PADDUSB/PADDUSW
xmm, xmm
2 2 1 2 2 1 MMX_ALU
PADDQ mm, mm 2 2 2 1 1 1 FP_MISC
PSUBQ mm, mm 2 2 2+1 1 1 2 FP_MISC
PADDQ/ PSUBQ
3
xmm,
xmm
662+122 2FP_MISC
PAND xmm, xmm 2 2 1 2 2 1 MMX_ALU
PANDN xmm, xmm 2 2 1 2 2 1 MMX_ALU
PAVG B / PAVGW x m m , xm m 2 2 2 2 M M X _A L U
PCMPEQB/PCMPEQD/
PCMPEQW xmm, xmm
2 2 1 2 2 1 MMX_ALU
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)