Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
C-8
PCMPGTB/PCMPGTD/PC
MPGTW xmm, xmm
2 2 1 2 2 1 MMX_ALU
PEXTRW r32, xmm, imm8 7 7 3 2 2 2 MMX_SHFT,
FP_MISC
PINSRW xmm, r32, imm8 4 4 1+1 2 2 2 MMX_SHFT,
MMX_MISC
PMADDWD xmm, xmm 9 8 3+1 2 2 2 FP_MUL
PMAX xmm, xmm 2 2 2 2 MMX_ALU
PMIN xmm, xmm 2 2 2 2 MMX_ALU
PMOVMSKB
3
r32, xmm 77 22 FP_MISC
PMULHUW/PMULHW/
PMULLW
3
xmm, xmm
983+122 2FP_MUL
PMULUDQ mm, mm 9 8 6 1 2 FP_MUL
PMULUDQ xmm, xmm 9 8 6+2 2 2 4 FP_MUL
POR xmm, xmm 2 2 1 2 2 1 MMX_ALU
PSADBW xmm, xmm 4 4 5+2 2 2 4 MMX_ALU
PSHUFD xmm, xmm, imm8 4 4 2+1 2 2 2 MMX_SHFT
PSHUFHW xmm, xmm,
imm8
2 2 1 2 2 1 MMX_SHFT
PSHUFLW xmm, xmm,
imm8
2 2 1 2 2 1 MMX_SHFT
PSLLDQ xmm, imm8 4 4 4 2 2 4 MMX_SHFT
PSLLW/PSLLD/PSLLQ
xmm, xmm/imm8
2 2 1+1 2 2 2 MMX_SHFT
PSRAW/PSRAD xmm,
xmm/imm8
2 2 1+1 2 2 2 MMX_SHFT
PSRLDQ xmm, imm8 4 4 4 2 2 4 MMX_SHFT
PSRLW/PSRLD/PSRLQ
xmm, xmm/imm8
2 2 1+1 2 2 2 MMX_SHFT
continued
Table C-2 Streaming SIMD Extension 2 128-bit Integer Instructions (continued)
Instruction Latency
1
Throughput
Execution
Unit
2

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)