Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-70
• Scalar floating-point registers may be accessed directly, avoiding
fxch and top-of-stack restrictions. On the Pentium 4 processor, the
floating-point register stack may be used simultaneously with XMM
registers. The same hardware is used for both kinds of instructions,
but the added name space may be beneficial.
• The cost of converting from floating point to integer with truncation
is significantly lower with Streaming SIMD Extensions 2 and
Streaming SIMD Extensions in the Pentium 4 processor than with
either changes to the rounding mode or the sequence prescribed in
the Example 2-23 above.
Assembly/Compiler Coding Rule 35. (M impact, M generality) Use scalar
Streaming SIMD Extensions 2, Streaming SIMD Extensions unless you need an
x87 feature. Most scalar SSE2 arithmetic operations have shorter latency then
their X87 counterpart and they eliminate the overhead associated with the
management of the X87 register stack.
Scalar SSE/SSE2 Performance on Intel Core Solo and Intel
Core Duo Processors
On Intel Core Solo and Intel Core Duo processors, the combination of
improved decoding and micro-op fusion allows instructions which were
formerly two, three, and four micro-ops to go through all decoders. As a
result, scalar SSE/SSE2 code can match the performance of x87 code
executing through two floating-point units. On Pentium M processors,
scalar SSE/SSE2 code can experience approximately 30% performance
degradation relative to x87 code executing through two floating-point
units.
In code sequences that have conversions from floating-point to integer,
divide single-precision instructions, or any precision change; x87 code
generation from a compiler typically writes data to memory in
single-precision and reads it again in order to reduce precision. Using
SSE/SSE2 scalar code instead of x87 code can generate a large
performance benefit using Intel NetBurst microarchitecture and a
modest benefit on Intel Core Solo and Intel Core Duo processors.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)