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Intel ARCHITECTURE IA-32 User Manual

Intel ARCHITECTURE IA-32
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IA-32 Intel® Architecture Optimization
A-10
Figure A-1 provides an example of a hotspots report by location.
Event-based Sampling
Event-based sampling (EBS) can be used to provide detailed
information on the behavior of the microprocessor as it executes
software. Some of the events that can be used to trigger sampling
include clockticks, cache misses, and branch mispredictions. The
VTune analyzer indicates where micro architectural events, specific to
the Pentium 4, Pentium M and Intel Xeon processors, occur the most
often. On Pentium M processors, the VTune analyzer can collect two
Figure A-1 Sampling Analysis of Hotspots by Location

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Intel ARCHITECTURE IA-32 Specifications

General IconGeneral
Instruction Setx86
Instruction Set TypeCISC
Memory SegmentationSupported
Operating ModesReal mode, Protected mode, Virtual 8086 mode
Max Physical Address Size36 bits (with PAE)
Max Virtual Address Size32 bits
ArchitectureIA-32 (Intel Architecture 32-bit)
Addressable Memory4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers8 x 80-bit
MMX Registers8 x 64-bit
SSE Registers8 x 128-bit
RegistersGeneral-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point UnitYes (x87)

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