Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Processor Family Overview
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In the first implementation of HT Technology, the physical execution
resources are shared and the architecture state is duplicated for each
logical processor. This minimizes the die area cost of implementing HT
Technology while still achieving performance gains for multithreaded
applications or multitasking workloads.
The performance potential due to HT Technology is due to:
• the fact that operating systems and user programs can schedule
processes or threads to execute simultaneously on the logical
processors in each physical processor
• the ability to use on-chip execution resources at a higher level than
when only a single thread is consuming the execution resources;
higher level of resource utilization can lead to higher system
throughput
Figure 1-6 Hyper-Threading Technology on an SMP
OM15152
Bus Interface
Execution Engine
Architectural
State
Architectural
State
Local APIC
Local APIC
System Bus
Execution Engine
Architectural
State
Architectural
State
Local APIC
Local APIC
Bus Interface

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)