Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-34
The two logical processors each have a complete set of architectural
registers while sharing one single physical processor's resources. By
maintaining the architecture state of two processors, an HT Technology
capable processor looks like two processors to software, including
operating system and application code.
By sharing resources needed for peak demands between two logical
processors, HT Technology is well suited for multiprocessor systems to
provide an additional performance boost in throughput when compared
to traditional MP systems.
Figure 1-6 shows a typical bus-based symmetric multiprocessor (SMP)
based on processors supporting Hyper-Threading Technology. Each
logical processor can execute a software thread, allowing a maximum of
two software threads to execute simultaneously on one physical
processor. The two software threads execute simultaneously, meaning
that in the same clock cycle an “add” operation from logical processor 0
and another “add” operation and load from logical processor 1 can be
executed simultaneously by the execution engine.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)