Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-26
best performance from a coding effort. An example of peeling out the
most favored target of an indirect branch with correlated branch history
is shown in Example 2-9.
Loop Unrolling
The benefits of unrolling loops are:
• Unrolling amortizes the branch overhead, since it eliminates
branches and some of the code to manage induction variables.
• Unrolling allows you to aggressively schedule (or pipeline) the loop
to hide latencies. This is useful if you have enough free registers to
keep variables live as you stretch out the dependence chain to
expose the critical path.
• Unrolling exposes the code to various other optimizations, such as
removal of redundant loads, common subexpression elimination,
and so on.
Example 2-9 A Peeling Technique to Reduce Indirect Branch Misprediction
function ()
{
int n = rand(); // random integer 0 to RAND_MAX
if( !(n & 0x01) ) n = 0;
// n will be 0 half the times
if (!n) handle_0(); // peel out the most common target
// with correlated branch history
else {
switch (n) {
case 1: handle_1(); break; // uncommon
case 3: handle_3(); break;// uncommon
default: handle_other(); // make the favored target in
// the fall-through path
}
}
}

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)