Intel ARCHITECTURE IA-32 User Manual

Mathematics of Prefetch Scheduling Distance E
E-11
memory to you cannot do much about it. Typically, data copy from one
space to another space, for example, graphics driver moving data from
writeback memory to write-combining memory, belongs to this
category, where performance advantage from prefetch instructions will
be marginal.
Example
As an example of the previous cases consider the following conditions
for computation latency and the memory throughput latencies. Assume
T
l
= 18 and T
b
= 8 (in front side bus cycles).

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)