Intel ARCHITECTURE IA-32 User Manual

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Contents
Introduction
Chapter 1 IA-32 Intel
®
Architecture Processor Family Overview
SIMD Technology.................................................................................................................... 1-2
Summary of SIMD Technologies ...................................................................................... 1-5
MMX™ Technology..................................................................................................... 1-5
Streaming SIMD Extensions....................................................................................... 1-5
Streaming SIMD Extensions 2.................................................................................... 1-6
Streaming SIMD Extensions 3.................................................................................... 1-6
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)........................................................ 1-7
Intel NetBurst
®
Microarchitecture............................................................................................ 1-8
Design Goals of Intel NetBurst Microarchitecture ............................................................ 1-8
Overview of the Intel NetBurst Microarchitecture Pipeline ............................................... 1-9
The Front End........................................................................................................... 1-11
The Out-of-order Core.............................................................................................. 1-12
Retirement ................................................................................................................ 1-12
Front End Pipeline Detail............................................................................................... 1-13
Prefetching................................................................................................................ 1-13
Decoder.................................................................................................................... 1-14
Execution Trace Cache ............................................................................................ 1-14
Branch Prediction ..................................................................................................... 1-15
Execution Core Detail..................................................................................................... 1-16
Instruction Latency and Throughput ......................................................................... 1-17
Execution Units and Issue Ports............................................................................... 1-18
Caches...................................................................................................................... 1-19
Data Prefetch............................................................................................................ 1-21
Loads and Stores...................................................................................................... 1-24
Store Forwarding ...................................................................................................... 1-25
Intel
®
Pentium
®
M Processor Microarchitecture................................................................... 1-26
The Front End........................................................................................................... 1-27
Data Prefetching....................................................................................................... 1-29

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)