Intel ARCHITECTURE IA-32 User Manual

iv
Out-of-Order Core..................................................................................................... 1-30
In-Order Retirement.................................................................................................. 1-31
Microarchitecture of Intel
®
Core™ Solo and Intel
®
Core™ Duo Processors........................ 1-31
Front End........................................................................................................................ 1-32
Data Prefetching............................................................................................................. 1-33
Hyper-Threading Technology................................................................................................ 1-33
Processor Resources and Hyper-Threading Technology............................................... 1-36
Replicated Resources............................................................................................... 1-36
Partitioned Resources .............................................................................................. 1-36
Shared Resources.................................................................................................... 1-37
Microarchitecture Pipeline and Hyper-Threading Technology........................................ 1-38
Front End Pipeline......................................................................................................... 1-38
Execution Core............................................................................................................... 1-39
Retirement...................................................................................................................... 1-39
Multi-Core Processors........................................................................................................... 1-39
Microarchitecture Pipeline and Multi-Core Processors................................................... 1-42
Shared Cache in Intel Core Duo Processors ................................................................. 1-42
Load and Store Operations....................................................................................... 1-42
Chapter 2 General Optimization Guidelines
Tuning to Achieve Optimum Performance .............................................................................. 2-1
Tuning to Prevent Known Coding Pitfalls................................................................................ 2-2
General Practices and Coding Guidelines.............................................................................. 2-3
Use Available Performance Tools..................................................................................... 2-4
Optimize Performance Across Processor Generations.................................................... 2-4
Optimize Branch Predictability.......................................................................................... 2-5
Optimize Memory Access................................................................................................. 2-5
Optimize Floating-point Performance............................................................................... 2-6
Optimize Instruction Selection.......................................................................................... 2-6
Optimize Instruction Scheduling....................................................................................... 2-7
Enable Vectorization......................................................................................................... 2-7
Coding Rules, Suggestions and Tuning Hints......................................................................... 2-8
Performance Tools.................................................................................................................. 2-9
Intel
®
C++ Compiler ......................................................................................................... 2-9
General Compiler Recommendations ............................................................................ 2-10
VTune™ Performance Analyzer..................................................................................... 2-10
Processor Perspectives ........................................................................................................ 2-11
CPUID Dispatch Strategy and Compatible Code Strategy ............................................. 2-13
Transparent Cache-Parameter Strategy......................................................................... 2-14
Threading Strategy and Hardware Multi-Threading Support.......................................... 2-14

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)