Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-2
For planning considerations of using the new SIMD integer instructions,
refer to “Checking for Streaming SIMD Extensions 2 Support” in
Chapter 3.
General Rules on SIMD Integer Code
The overall rules and suggestions are as follows:
• Do not intermix 64-bit SIMD integer instructions with x87
floating-point instructions. See “Using SIMD Integer with x87
Floating-point” section in this chapter. Note that all of the SIMD
integer instructions can be intermixed without penalty.
• When writing SSE2 code that works with both integer and
floating-point data, use the subset of SIMD convert instructions or
load/store instructions to ensure that the input operands in XMM
registers contain properly defined data type to match the instruction.
Code sequences containing cross-typed usage will produce the same
result across different implementations, but will incur a significant
performance penalty. Using SSE or SSE2 instructions to operate on
type-mismatched SIMD data in the XMM register is strongly
discouraged.
• Use the optimization rules and guidelines described in Chapter 2
and Chapter 3 that apply to the Pentium 4, Intel Xeon and
Pentium M processors.
• Take advantage of hardware prefetcher where possible. Use prefetch
instruction only when data access patterns are irregular and prefetch
distance can be pre-determined. (for details, refer to Chapter 6,
“Optimizing Cache Usage”).
• Emulate conditional moves by using masked compares and logicals
instead of using conditional branches.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)