Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-77
(model 9) does incur a penalty. This is because every operation on a
partial register updates the whole register. However, this does mean that
there may be false dependencies between any references to partial
registers.
Example 2-24 demonstrates a series of false and real dependencies
caused by referencing partial registers.
If instructions 4 and 6 (see Example 2-24) are changed to use a
movzx
instruction instead of a
mov, then the dependences of instructions 4 on 2
(and transitively 1 before it), and instructions 6 on 5 are broken. This
creates two independent chains of computation instead of one serial one.
In a tight loop with limited parallelism, the resulting optimization can
yield several percent performance improvement.
Example 2-24 Dependencies Caused by Referencing Partial Registers
1: add ah, bh
2: add al, 3 ; instruction 2 has a false dependency on 1
3: mov bl, al ; depends on 2, but the dependence is real
4: mov ah, ch ; instruction 4 has a false dependency on 2
5: sar eax, 16 ; this wipes out the al/ah/ax part, so the
; result really doesn't depend on them programatically,
; but the processor must deal with the real dependency on
; al/ah/ax
6: mov al, bl ; instruction 6 has a real dependency on 5
7: add ah, 13 ; instruction 7 has a false dependency on 6
8: imul dl ; instruction 8 has a false dependency on 7
; because al is implicitly used
9: mov al, 17 ; instruction 9 has a false dependency on 7
; and a real dependency on 8
10: imul cx : implicitly uses ax and writes to dx, hence
; a real dependency

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)