EasyManuals Logo

Intel ARCHITECTURE IA-32 User Manual

Intel ARCHITECTURE IA-32
568 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #105 background imageLoading...
Page #105 background image
General Optimization Guidelines 2
2-33
If a variable is known not to change between when it is stored and when
it is used again, the register that was stored can be copied or used
directly. If register pressure is too high, or an unseen function is called
before the store and the second load, it may not be possible to eliminate
the second load.
Assembly/Compiler Coding Rule 17. (H impact, M generality) Pass
parameters in registers instead of on the stack where possible. Passing
arguments on the stack is a case of store followed by a reload. While this
sequence is optimized in IA-32 processors by providing the value to the load
directly from the memory order buffer without the need to access the data
cache, floating point values incur a significant latency in forwarding. Passing
floating point argument in (preferably XMM) registers should save this long
latency operation.
Parameter passing conventions may limit the choice of which
parameters are passed in registers versus on the stack. However, these
limitations may be overcome if the compiler has control of the
compilation of the whole binary (using whole-program optimization).
Store-to-Load-Forwarding Restriction on Size and
Alignment
Data size and alignment restrictions for store-forwarding apply to the
Pentium 4, Intel Xeon and Pentium M processor. The performance
penalty from violating store-forwarding restrictions is less for
Pentium M processors than that for Pentium 4 processors.
This section describes these restrictions in all cases. It prescribes
recommendations to prevent the non-forwarding penalty. Fixing this
problem for Pentium 4 and Intel Xeon processors also fixes problem on
Pentium M processors.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel ARCHITECTURE IA-32 and is the answer not in the manual?

Intel ARCHITECTURE IA-32 Specifications

General IconGeneral
Instruction Setx86
Instruction Set TypeCISC
Memory SegmentationSupported
Operating ModesReal mode, Protected mode, Virtual 8086 mode
Max Physical Address Size36 bits (with PAE)
Max Virtual Address Size32 bits
ArchitectureIA-32 (Intel Architecture 32-bit)
Addressable Memory4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers8 x 80-bit
MMX Registers8 x 64-bit
SSE Registers8 x 128-bit
RegistersGeneral-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point UnitYes (x87)

Related product manuals