Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
3-8
Example 3-7 Identification of SSE3 by the OS
Considerations for Code Conversion to SIMD
Programming
The VTune Performance Enhancement Environment CD provides tools
to aid in the evaluation and tuning. But before implementing them, you
need answers to the following questions:
1. Will the current code benefit by using MMX technology, Streaming
SIMD Extensions, Streaming SIMD Extensions 2, or Streaming
SIMD Extensions 3?
2. Is this code integer or floating-point?
3. What integer word size or floating-point precision is needed?
4. What coding techniques should I use?
5. What guidelines do I need to follow?
6. How should I arrange and align the datatypes?
Figure 3-1 provides a flowchart for the process of converting code to
MMX technology, Streaming SIMD Extensions, or Streaming SIMD
Extensions 2.
bool SSE3_SIMD_SupportCheck() {
_try {
__asm addsubpd xmm0, xmm0 ; SSE3}
_except(EXCEPTION_EXECUTE_HANDLER) {
if _exception_code()==STATUS_ILLEGAL_INSTRUCTION)
/* SSE3not supported */
return (false);
}
/* SSE3 SIMD and FISTTP instructions are supported */
return (true);
}

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)