Intel ARCHITECTURE IA-32 User Manual

Mathematics of Prefetch Scheduling Distance E
E-7
The iteration latency is approximately equal to the computation latency
plus the memory leadoff latency (includes cache miss latency, chipset
latency, bus arbitration, and so on.) plus the data transfer latency where
transfer latency= number of lines per iteration * line burst latency.
This means that the decoupled memory and execution are ineffective to
explore the parallelism because of flow dependency. That is the case
where prefetch can be useful by removing the bubbles in either the
execution pipeline or the memory pipeline.
With an ideal placement of the data prefetching, the iteration latency
should be either bound by execution latency or memory latency, that is
il = maximum(T
c
, T
b
).
Compute Bound (Case:Tc >= T
l
+ T
b
)
Figure E-3 represents the case when the compute latency is greater than
or equal to the memory leadoff latency plus the data transfer latency. In
this case, the prefetch scheduling distance is exactly 1; i.e., prefetch data
one iteration ahead is good enough. The data for loop iteration i can be
prefetched during loop iteration i-1, the δ
f
symbol between front-side
bus and execution pipeline indicates the data flow dependency.
Figure E-3 Compute Bound Execution Pipeline
Front-Side Bus
Execution pipeline
T
c
T
l
T
b
Iteration i
Iteration i+1
T
c
T
l
T
b
Execution cycles
δ
f

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)