Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
6-8
The Prefetch Instructions – Pentium 4 Processor
Implementation
Streaming SIMD Extensions include four flavors of prefetch
instructions, one non-temporal, and three temporal. They correspond to
two types of operations, temporal and non-temporal.
The non-temporal instruction is
prefetchnta Fetch the data into the second-level cache, minimizing
cache pollution.
The temporal instructions are
prefetcht0 Fetch the data into all cache levels, that is, to the
second-level cache for the Pentium 4 processor.
prefetcht1 Identical to prefetcht0
prefetcht2
Identical to prefetcht0
Prefetch and Load Instructions
The Pentium 4 processor has a decoupled execution and memory
architecture that allows instructions to be executed independently with
memory accesses if there are no data and resource dependencies.
Programs or compilers can use dummy load instructions to imitate
prefetch functionality, but preloading is not completely equivalent to
prefetch instructions. Prefetch instructions provide a greater
performance than preloading.
NOTE. At the time of prefetch, if the data is already
found in a cache level that is closer to the processor
than the cache level specified by the instruction, no
data movement occurs.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)