Intel ARCHITECTURE IA-32 User Manual

Power Optimization for Mobile Usages 9
9-3
to accommodate demand and adapt power consumption. The interaction
between the OS power management policy and performance history is
described below:
1. Demand is high and the processor works at its highest possible
frequency (P0).
2. Demand decreases, which the OS recognizes after some delay; the
OS sets the processor to a lower frequency (P1).
3. The processor decreases frequency and processor utilization
increases to the most effective level, 80-90% of the highest possible
frequency. The same amount of work is performed at a lower
frequency.
4. Demand decreases and the OS sets the processor to the lowest
frequency, sometimes called Low Frequency Mode (LFM).
5. Demand increases and the OS restores the processor to the highest
frequency.
Figure 9-1 Performance History and State Transitions
CPU demand Frequency
& Power
1
2
3
4
5

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)