Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-12
corresponding task to use its designated buffer. Thus, the producer and
consumer tasks execute in parallel in two threads. As long as the data
generated by the producer reside in either the first or second level cache
of the same core, the consumer can access them without incurring bus
traffic. The scheduling of the interlaced producer-consumer model is
shown in Figure 7-4.
Example 7-3 shows the basic structure of a thread function that can be
used in this interlaced producer-consumer model.
Figure 7-4 Interlaced Variation of the Producer Consumer Model
P(2)
P(1)
P(2)
P(1) C(1)
C(2)
C(1)
C(2)
P(1)
Thread 0
Thread 1

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)