Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-47
Table B-2 Metrics That Utilize Replay Tagging Mechanism
Replay Metric Tags
1
Bit field to
set:
IA32_PEBS_
ENABLE
Bit field
to set:
MSR_
PEBS_
MATRIX_
VERT Additional MSR
See Event
Mask
Parameter
for
Replay_
event
1stL_cache_load_
miss_retired
Bit 0, BIT 24,
BIT 25
Bit 0 None NBOGUS
2ndL_cache_load_
miss_retired
Bit 1, BIT 24,
BIT 25
Bit 0 None NBOGUS
continued
DTLB_load_miss_
retired
Bit 2, BIT 24,
BIT 25
Bit 0 None NBOGUS
DTLB_store_miss_
retired
Bit 2, BIT 24,
BIT 25
Bit 1 None NBOGUS
DTLB_all_miss_
retired
Bit 2, BIT 24,
BIT 25
Bit 0, Bit 1 None NBOGUS
Tagged_mispred_
branch
Bit 15, Bit 16,
Bit 24, Bit 25
Bit 4 None NBOGUS
MOB_load_
replay_retired
Bit 9, BIT 24,
BIT 25
Bit 0 Select MOB_load_
replay and set the
PARTIAL_DATA and
UNALGN_ADDR bits
NBOGUS
Split_load_
retired
Bit 10, BIT
24, BIT 25
Bit 0 Select
Load_port_replay
event on
SAAT_CR_ESCR1 and
set SPLIT_LD bit
NBOGUS
Split_store_
retired
Bit 10, BIT
24, BIT 25
Bit 1 Select Store_port_
replay event on
SAAT_CR_ESCR0 and
set SPLIT_ST bit
NBOGUS
1. Certain kinds of μops cannot be tagged. These include I/O operations, UC and locked accesses, returns, and far
transfers.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)