Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-20
Unpacking/interleaving 64-bit Data in 128-bit Registers
The punpcklqdq/punpchqdq instructions interleave the low/high-order
64-bits of the source operand and the low/high-order 64-bits of the
destination operand and writes them to the destination register. The
high/low-order 64-bits of the source operands are ignored.
Example 4-13 Swap Using 3 Instructions
/* Goal: Swap the values in word 6 and word 1 */
/* Instruction Result */
| 7| 6| 5| 4| 3| 2| 1| 0|
PSHUFD (3,0,1,2)| 7| 6| 1| 0| 3| 2| 5| 4|
PSHUFHW (3,1,2,0)| 7| 1| 6| 0| 3| 2| 5| 4|
PSHUFD (3,0,1,2)| 7| 1| 5| 4| 3| 2| 6| 0|
Example 4-14 Reverse Using 3 Instructions
/* Goal: Reverse the order of the words */
/* Instruction Result */
| 7| 6| 5| 4| 3| 2| 1| 0|
PSHUFLW (0,1,2,3)| 7| 6| 5| 4| 0| 1| 2| 3|
PSHUFHW (0,1,2,3)| 4| 5| 6| 7| 0| 1| 2| 3|
PSHUFD (1,0,3,2)| 0| 1| 2| 3| 4| 5| 6| 7|

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)