Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-10
Producer-Consumer Threading Models
Figure 7-3 illustrates the basic scheme of interaction between a pair of
producer and consumer threads. The horizontal direction represents
time. Each block represents a task unit, processing the buffer assigned to
a thread. The gap between each task represents synchronization
overhead. The decimal number in the parenthesis represents a buffer
index. On an Intel Core Duo processor, the producer thread can store
data in the second-level cache to allow the consumer thread to continue
work requiring minimal bus traffic.
The basic structure to implement the producer and consumer thread
functions with synchronization to communicate buffer index is shown in
Example 7-2.
Figure 7-3 Execution of Producer-consumer Threading Model on a Multi-core
Processor
Main
Thread
P(2) P(1)P(2)P(1)
C(1)C(2)C(1) C(2)
P(1)
P: producer
C: consumer

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)