Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-19
Packed Shuffle Word for 128-bit Registers
The pshuflw/pshufhw instruction performs a full shuffle of any source
word field within the low/high 64 bits to any result word field in the
low/high 64 bits, using an 8-bit immediate operand; the other high/low
64 bits are passed through from the source operand.
The
pshufd instruction performs a full shuffle of any double-word field
within the 128-bit source to any double-word field in the 128-bit result,
using an 8-bit immediate operand.
No more than 3 instructions, using
pshuflw/pshufhw/pshufd, are
required to implement some common data shuffling operations.
Broadcast, Swap, and Reverse are illustrated in Example 4-12,
Example 4-13, and Example 4-14, respectively.
Example 4-11 pshuf Instruction Code
; Input:
; edi source value
; Output:
; MM1 MM register containing re-arranged words
movq mm0, [edi]
pshufw mm1, mm0, 0x1b
Example 4-12 Broadcast Using 2 Instructions
/* Goal: Broadcast the value from word 5 to all words */
/* Instruction Result */
| 7| 6| 5| 4| 3| 2| 1| 0|
PSHUFHW (3,2,1,1)| 7| 6| 5| 5| 3| 2| 1| 0|
PSHUFD (2,2,2,2)| 5| 5| 5| 5| 5| 5| 5| 5|

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)