Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Processor Family Overview
1-27
The Intel Pentium M processor microarchitecture is designed for lower
power consumption. There are other specific areas of the Pentium M
processor microarchitecture that differ from the Intel NetBurst
microarchitecture. They are described next. A block diagram of the Intel
Pentium M processor is shown in Figure 1-5.
The Front End
The Intel Pentium M processor uses a pipeline depth that enables high
performance and low power consumption. It’s shorter than that of the
Intel NetBurst microarchitecture.
The Intel Pentium M processor front end consists of two parts:
• fetch/decode unit
• instruction cache
Figure 1-5 The Intel Pentium M Processor Microarchitecture
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Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)