Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-47
Mixing Code and Data
The Pentium 4 processor’s aggressive prefetching and pre-decoding of
instructions has two related effects:
• Self-modifying code works correctly, according to the Intel
architecture processor requirements, but incurs a significant
performance penalty. Avoid self-modifying code.
• Placing writable data in the code segment might be impossible to
distinguish from self-modifying code. Writable data in the code
segment might suffer the same performance penalty as
self-modifying code.
Assembly/Compiler Coding Rule 26. (M impact, L generality) If (hopefully
read-only) data must occur on the same page as code, avoid placing it
immediately after an indirect jump. For example, follow an indirect jump with
its mostly likely target, and place the data after an unconditional branch.
Tuning Suggestion 1. In rare cases, a performance problem may be noted due
to executing data on a code page as instructions. The condition where this is
very likely to happen is when execution is following an indirect branch that is
not resident in the trace cache. If a performance problem is clearly due to this
cause, try moving the data elsewhere or inserting an illegal opcode or a
pause
instruction immediately following the indirect branch. The latter two
alternatives may degrade performance in some circumstances.
Assembly/Compiler Coding Rule 27. (H impact, L generality) Always put
code and data on separate pages. Avoid self-modifying code wherever possible.
If code is to be modified, try to do it all at once and make sure the code that
performs the modifications and the code being modified are on separate 4 KB
pages or on separate aligned 1 KB subpages.
Self-modifying Code
Self-modifying code (SMC) that ran correctly on Pentium III processors
and prior implementations will run correctly on subsequent
implementations, including Pentium 4 and Intel Xeon processors. SMC

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)