Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-37
These transformations, in general, increase the number of instructions
required to perform the desired operation. For Pentium II, Pentium III,
and Pentium 4 processors, the benefit of avoiding forwarding problems
outweighs the performance penalty due to the increased number of
instructions, making the transformations worthwhile.
Supplemental Techniques for Avoiding Cache Line Splits
Some video processing applications sometimes cannot avoid loading
data from memory address that are aligned to 16 byte boundary. An
example of this situation is when each line in a video frame is averaged
by shifting horizontally half a pixel. Example 4-28 shows a common
operation in video processing that loads data from memory address not
aligned to 16 byte boundary. As video processing traverses each line in
the video frame, it will experience at least a cache line split for each
64 bytes loaded from memory.
Example 4-28 An Example of Video Processing with Cache Line Splits
// Average half-pels horizonally (on // the “x” axis),
// from one reference frame only.
nextLinesLoop:
movdqu xmm0, XMMWORD PTR [edx] // may not be 16B aligned
movdqu xmm0, XMMWORD PTR [edx+1]
movdqu xmm1, XMMWORD PTR [edx+eax]
movdqu xmm1, XMMWORD PTR [edx+eax+1]
pavgbxmm0, xmm1
pavgbxmm2, xmm3
movdqaXMMWORD PTR [ecx], xmm0
movdqaXMMWORD PTR [ecx+eax], xmm2
// (repeat ...)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)