Intel ARCHITECTURE IA-32 User Manual

Power Optimization for Mobile Usages 9
9-7
• In an Intel Core Solo or Duo processor, after staying in C4 for an
extended time, the processor may enter into a Deep C4 state to save
additional static power..
The processor reduces voltage to the minimum level required to safely
maintain processor context. Although exiting from a deep C4 state may
require warming the cache, the performance penalty may be low enough
such that the benefit of longer battery life outweighs the latency of the
deep C4 state.
Guidelines for Extending Battery Life
Follow the guidelines below to optimize to conserve battery life and
adapt for mobile computing usage:
• Adopt a power management scheme to provide just-enough (not the
highest) performance to achieve desired features or experiences.
• Avoid using spin loops.
• Reduce the amount of work the application performs while
operating on a battery.
• Take advantage of hardware power conservation features using
ACPI C3 state type and coordinate processor cores in the same
physical processor.
• Implement transitions to and from system sleep states (S1-S4)
correctly.
• Allow the processor to operate at a higher-numbered P-state (lower
frequency but higher efficiency in performance-per-watt) when
demand for processor performance is low.
• Allow the processor to enter higher-numbered ACPI C-state type
(deeper, low-power states) when user demand for processor activity
is infrequent.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)