Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Processor Family Overview
1-19
Caches
The Intel NetBurst microarchitecture supports up to three levels of
on-chip cache. At least two levels of on-chip cache are implemented in
processors based on the Intel NetBurst microarchitecture. The Intel
Xeon processor MP and selected Pentium and Intel Xeon processors
may also contain a third-level cache.
The first level cache (nearest to the execution core) contains separate
caches for instructions and data. These include the first-level data cache
and the trace cache (an advanced first-level instruction cache). All other
caches are shared between instructions and data.
Figure 1-4 Execution Units and Ports in the Out-Of-Order Core
OM15151
ALU 0
Double
Speed
Port 0
ADD/SUB
Logic
Store Data
Branches
FP Move
FP Store Data
FXCH
ALU 1
Double
Speed
ADD/SUB Shift/Rotate
FP
Execute
FP_ADD
FP_MUL
FP_DIV
FP_MISC
MMX_SHFT
MMX_ALU
MMX_MISC
Port 1
Memory
Store
Memory
Load
All Loads
Prefetch
Port 2
Port 3
Store
Address
FP
Move
Integer
Operation
Normal
Speed
Note:
FP_ADD refers to x87 FP, and SIMD FP add and subtract operations
FP_MUL refers to x87 FP, and SIMD FP multiply operations
FP_DIV refers to x87 FP, and SIMD FP divide and square root operations
MMX_ALU refers to SIMD integer arithmetic and logic operations
MMX_SHFT handles Shift, Rotate, Shuffle, Pack and Unpack operations
MMX_MISC handles SIMD reciprocal and some integer operations

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)