Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-25
Absolute Value
Use Example 4-18 to compute |x|, where x is signed. This example
assumes signed words to be the operands.
movq MM2, MM0 ; make a copy of source1 (A)
pcmpgtw MM0, MM1 ; create mask of
; source1>source2 (A>B)
movq MM4, MM2 ; make another copy of A
pxor MM2, MM1 ; create the intermediate value of
; the swap operation - xor(A,B)
pand MM2, MM0 ; create a mask of 0s and xor(A,B)
; elements. Where A>B there will
; be a value xor(A,B) and where
; A<=B there will be 0.
pxor MM4, MM2 ; minima-xor(A, swap mask)
pxor MM1, MM2 ; maxima-xor(B, swap mask)
psubw MM1, MM4 ; absolute difference =
; maxima-minima
Example 4-18 Computing Absolute Value
; Input:
; MM0 signed source operand
; Output:
; MM1 ABS(MMO)
pxor MM1, MM1 ; set MM1 to all zeros
psubw MM1, MM0 ; make each MM1 word contain the
; negative of each MM0 word
pmaxsw MM1, MM0 ; MM1 will contain only the positive
; (larger) values - the absolute value
Example 4-17 Absolute Difference of Signed Numbers (continued)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)