Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-68
Assembly/Compiler Coding Rule 33. (H impact, L generality) Minimize the
number of changes to the precision mode.
Improving Parallelism and the Use of FXCH
The x87 instruction set relies on the floating point stack for one of its
operands. If the dependence graph is a tree, which means each
intermediate result is used only once and code is scheduled carefully, it
is often possible to use only operands that are on the top of the stack or
in memory, and to avoid using operands that are buried under the top of
the stack. When operands need to be pulled from the middle of the
stack, an
fxch instruction can be used to swap the operand on the top of
the stack with another entry in the stack.
The
fxch instruction can also be used to enhance parallelism.
Dependent chains can be overlapped to expose more independent
instructions to the hardware scheduler. An
fxch instruction may be
required to effectively increase the register name space so that more
operands can be simultaneously live.
Note, however, that
fxch inhibits issue bandwidth in the trace cache. It
does this not only because it consumes a slot, but also because of issue
slot restrictions imposed on
fxch. If the application is not bound by
issue or retirement bandwidth,
fxch will have no impact.
The Pentium 4 processor’s effective instruction window size is large
enough to permit instructions that are as far away as the next iteration to
be overlapped. This often obviates the need to use
fxch to enhance
parallelism.
The
fxch instruction should be used only when it’s needed to express an
algorithm or to enhance parallelism. If the size of register name space is
a problem, the use of XMM registers is recommended (see the section).
Assembly/Compiler Coding Rule 34. (M impact, M generality) Use fxch
only where necessary to increase the effective name space.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)